教育背景：
20011.9-2015.9：法國格勒諾布爾-阿爾卑斯大學，博士；
2004.9-2008.6：四川大學微電子系，本科。
工作簡曆：
2019.12至今：中國科學院微电子研究所，副研究員；
1. 2020-2022，國家自然科學基金青年項目，“三維單片集成SRAM重離子單粒子效應研究”，11905287，24萬，在研，主持;
2. 2021-2022，矽器件重點實驗室基金，“三維單片集成組合電路單粒子軟錯誤研究”，80萬，主持；
3. 2020-2022，高技術項目，“SOI FinFET新結構器件研究”，200萬元，在研，骨幹人員；
4. 國家自然科學基金重點項目“集成電路輻照效應與抗輻照技術研究”，200萬，結題，參與；
5. 国家自然科学基金“纳米级集成电路SET軟錯誤率分析技術研究”，No. 61006070，20萬，結題，參與。期刊
1. R. Cheng, Y. Sun, Y. M. Qu, W. Liu, F. Y. Liu, J. F Gao, B. Chen, N. Xu and J. W. Lu, “Nano-scaled Transistor's Performance and Reliability Characterization at Nano-second Regime,” Science China Information Sciences, 2020（已接收）.
2. 張峰源，劉凡宇，李博，李彬鴻，張旭，羅家�。n鄭生，張青竹“考慮背柵偏置的FOI FinFET電流模型研究，”《半導體技術》，2020（已接收）.
3. 張峰源，李博，劉凡宇，楊燦，黃楊，張旭，羅家�。n鄭生，“FinFET總劑量效應研究進展，”《微電子學》，2020（已接收）.
4. Y. D. Li, Q. Z. Zhang, F. Y. Liu, Z. H. Zhang, F. Y. Zhang, H. B. Zhao, Bo Li and J. Yan, “X-ray Irradiation Induced Degradation in Hf0.5Zr0.5O2 FDSOI nMOSFETs,” Rare Metals, 2020 (accepted).
5. J. T. Gao, Q. Zhang, B. Li, K. Xi, Bo. Li, F. Y. Liu, F. Z. Zhao, C. B. Zeng, J. J. Luo, Z. S. Han and Gang. Guo, “Proton and light ions induced SEU effect in a SOI SRAM with gold plated lid,” Microelectronics Reliability, 100-101, 2019.
6. M. S. Parihar, F. Y. Liu, C. Navarroa, S. Barraud, M. Bawedin, I. Ionica, A. Kranti and S. Cristoloveanu, “Back-gate effects and mobility characterization in junctionless transistor,” Solid-State Electronics, vol. 125, pp. 154~160, 2016.
7. F. Y. Liu, H. Z. Liu, B. W. Liu and Y. F. Guo, “An analytical model for nanowire junctionless SOI FinFETs considering three-dimensional coupling effect,” Chin. Phys. B, vol. 25, no. 4, pp. 047305, 2016.
8. F. Y. Liu, I. Ionica, M. Bawedin and S. Cristoloveanu, “Parasitic bipolar effect in ultra-thin FD SOI MOSFETs,” Solid-State Electronics, vol. 112, pp. 29~36, 2015.
9. F. Y. Liu, I. Ionica, M. Bawedin and S. Cristoloveanu, “Extraction of the Parasitic Bipolar Gain Using the Back-gate in Ultra-thin FD SOI MOSFETs,” IEEE Elec. Dev. Lett., vol. 32, no. 2, pp. 96~98, 2015.
10. B. W. Liu and F. Y. Liu, “TCAD Simulation Study of the Single-Event Effects in Silicon nanowire Transistors,” IEEE Trans. Dev and Mat. Reli., vol. 15, no. 2, pp. 410~416, 2015.
11. S-J. Chang, M. Bawedin, Y. F. Guo, F. Y. Liu, K. Akarvardar, J-H. Lee, J-H. Lee, I. Ionica and S. Cristoloveanu, “Enhanced coupling effects in vertical double-gate FinFETs,” Solid-State Electronics, vol. 97, pp. 88~98, 2014.
12. F. Y. Liu, A. Diab, I. Ionica, K. Akarvardar, C. Hobbs, T. Ouisse, X. Mescot and S. Cristoloveanu, “Characterization of Heavily Doped SOI wafers under Pseudo-MOSFETs Configuration,” Solid-State Electronics, vol. 90, pp.65~72, 2013.
13. F. Y. Liu, H. Z. Liu, B. Liang, B. W. Liu, J. J. Chen. “Impact of Doping Concentration in P+ Deep Wells on Charge Sharing in 90nm CMOS Technology,” Acta Physica Sinica, vol. 60, no.4, pp. 046106-1~046106-8, 2011.
14. H. Z. Liu, F. Y. Liu, B. Liang, B. W. Liu, “Impact of STI Depth on Charge Sharing in 90nm CMOS Technology,” Journal of National University of Defense Technology, vol. 33, no. 2, pp. 136~139, 2011.
15. J. R. Qin, S. M. Chen, B. W. Liu, F. Y. Liu and J. J. Chen, “The Effect of P+ Deep Well Doping on SET Pulse Propagation,” Science China Technological Sciences, vol. 55, no. 3, pp. 665~672, 2012.
16. J. J. Chen, S. M. Chen, B. Liang and F. Y. Liu, “Single Event Transient Pulse Attenuation Effect In Three Transistors Inverter Chain,” Science China Technological Sciences, vol. 55, pp. 867~871, 2012.
17. J. J. Chen, S. M. Chen, B. Liang and F. Y. Liu, “Radiation Hardened by Design Techniques to Reduce Single Event Transient Pulse Width Based on the Physical Mechanism,” Microelectronic Reliability, vol. 52, no. 6, pp. 1227~1232, 2012.
18. S. M. Chen, J. J. Chen, Y. Q. Chi and F. Y. Liu, Y. B. He. “Modeling to predict the time evolution of negative bias temperature instability (NBTI) induced single event transient pulse broadening,” Science China Technological Sciences, vol. 55, no. 4, pp. 1101~1106, 2012.
會議
1. J. J. Zhang, F. Y. Liu, B. Li, B. H. Li, Y. Huang, C. Yang, G. Q. Wang, R. W. Wang, J. J. Luo and Z. S. Han, “Temperature dependence of single event upset of monolithic 3-D integrated 6T SRAM based on a 22 nm FD-SOI technology,” ESREF 2020 (accepted).
2. Y. X. Chen, J. Liu, K. Xiao, A. Zaslavsky, S. Cristoloveanu, F. Y. Liu, B. H. Li, B. Li and J. Wan, “Unijunction Transistor Based on Silicon-on-insulator Substrate,” IWJT2020 (submitted).
3. X. Zhang, F. Y. Liu, B. Li, J. J. Luo, Z. S. Han, M. Arsalan, J. Wan and S. Cristoloveanu, “Pseudo-MOSFET transient behavior: experiments, model and substrate effect,” EuroSOI & ULIS 2020 (accepted).
4. M. Arsalan, J. Liu, A. Zaslavsky, S. Cristoloveanu, F. Y. Liu, B. H. Li, B. Li and J. Wan, “Suppressing crosstalk in the photoelectron in-situ sensing device (PISD) by double SOI,” EuroSOI & ULIS 2020 (accepted).
5. G. Q. Wang, F. Y. Liu, B. Li, Y. Huang, Y. C. Wang, C. N. Wu, J. M. Zhang, J. J. Luo, Z. S. Han and S. Cristoloveanu, “Revisited parasitic bipolar effect in FDSOI MOSFETs: Mechanism, current gain extraction and its circuit applications,” EuroSOI & ULIS 2020 (accepted).
6. F. Y. Zhang, F. Y. Liu, B. Li, B. H. Li, C. Yang, R. W. Wang, J. J. Luo and Z. S. Han, “The Current Model for FOI FinFETs with Back-Gate Bias,” EuroSOI & ULIS 2020 (accepted).
7. Y. Huang, F. Y. Liu, B. H. Li, B. Li, J. T. Gao, L. Wang, X. H. Su, H. N. Liu, Z. S. Han and J. J. Luo, “Radiation-induced Degradation Mechanism in Double-SOI pMOSFETs”, Proceedings of RADECS 2019, France.
8. M. S. Parihar, F. Y. Liu, C. Navarroa, S. Barraud, M. Bawedin, I. Ionica, A. Kranti and S. Cristoloveanu, “Back-gate effects and detailed characterization of junctionless transistor,” Proceedings of ESSDERC 2015, Wien, Austria, 2015, pp. 282~285.
9. F. Y. Liu, I. Ionica, M. Bawedin and S. Cristoloveanu, “A simple compact model for carrier distribution and its application in single-, double- and triple-gate junctionless transistors,” Proceedings of EuroSOI & ULIS, Bologna, Italy, 2015.
10. F. Y. Liu, I. Ionica, M. Bawedin and S. Cristoloveanu, “Effect of back-gate on parasitic bipolar effect in FD SOI MOSFETs,” Proceedings of IEEE S3S Conference, San Francisco, USA, 2014, pp. 85~86.
11. F. Y. Liu, I. Ionica, M. Bawedin and S. Cristoloveanu, “Parasitic bipolar effect in advanced FD SOI MOSFETs: experimental evidence and gain extraction,” Proceedings of EuroSOI 2014, Tarragona, Spain, 2014.
12. F. Y. Liu, L. Dicioccio, I. Ionica, Y. F. Guo and S. Cristoloveanu, “A New Extracting Method for Estimating the Bonding Quality of Metal Bonded Wafers,” Proceedings of EuroSOI 2013, Paris, France, 2013.
13. Y. F. Guo, F. Y. Liu, S. J. Chang, J. F. Yao and S. Cristoloveanu, “An analytical model of back-gate coupling effects in vertical double-gate SOI MOSFETs,” Proceeding of EuroSOI 2013, Paris, France, 2013.
14. F. Y. Liu, A. Diab, I. Ionica, K. Akarvardar, C. Hobbs, T. Ouisse, X. Mescot and S. Cristoloveanu, “Transport Properties in Heavily Doped SOI Wafers,” Proceeding of EuroSOI 2012, Montpellier, France, 2012.
15. S. Cristoloveanu, I. Ionica, A. Diab and F. Y. Liu, “The Pseudo-MOSFET : principles and recent trends,” (invited), 12th Int. Symposium on High Purity Silicon, 222nd Meeting of the Electrochemical Soc., Honolulu, Hawaii, USA, 2012.
16. C. Q. Xu, P. Batude, B. Sklenard, M. Vinet, M. Mouis, B. Previtali, F. Y. Liu, J. Guerrero, K. Yckache, P. Rivallin, V. Mazzocchi, S. Cristoloveanu, O. Faynot and T. Poiroux, “FDSOI: A solution to suppress boron deactivation in low temperature processed devices,” 12th International Workshop on Junction Technology (IWJT), Shanghai, 2012, pp. 69~72.
譯著
1.《可靠性物理與工程-失效時間模型（第3版）》
2.《抗輻射集成電路設計》1. 國防科學技術大學優秀畢業生，長沙，中國，2016；
2. 湖南省优秀硕士学位論文，长沙，中国，2013；
3. 國防科學技術大學優秀博士生創新資助，長沙，中國，2012；
4. 国防科学技术大学优秀硕士学位論文，长沙，中国，2012。
人才隊伍