教育背景
2007-2011：中國科學院微电子研究所，微电子学与固体电子学专业，工学博士
2004-2007：遼甯大學物理學院，微電子學與固體電子學專業，理學碩士
2000-2004：遼甯大學物理學院，電子科學與技術專業，工學學士
工作簡曆
2018年-至今：中國科學院微电子研究所，集成電路先導工藝研發中心，正高級工程師，博士导师，入选中科院“院级高层次引进人才”，从事亞10納米三維器件與集成技術研究
2011-2017年：新加坡聯華電子公司（UMC），主任工程師，從事納米CMOS器件和集成技術研究，主要負責邏輯産品、SRAM Macro以及eHV制程研發和平台建設
1. 2018年，02专项子课题“锗/锗硅高迁移率沟道三维器件及关键共性技术”，核心骨干
2. 2019年，中國科學院“集成电路新器件与先导工艺”课题，子课题负责人
3. 2019年，北京市科委“水平堆叠环栅器件研制与新型沟道原型器件研究”课题，课题负责人
4. 2019年，中科院微电子所所长基金“SiGe高迁移率沟道FinFET集成技术研究”，课题负责人
5. 2020年，北京市自然基金面上项目“鍺硅高迁移率沟道FinFET器件关键集成技术研究”，项目负责人
6. 2021年，国家自然科学基金面上项目“适用于三维FinFET器件的高浓度鍺硅高迁移率沟道制备和钝化技术及机理研究”，项目负责人
1. Zhiqian Zhao, Yongliang Li*, Shihai Gua, et al., High crystal quality strained Si0.5Ge0.5 layer with a thickness of up to 50 nm grown on the three-layer SiGe strain relaxed buffer. Materials Science in Semiconductor Processing, 2019, 99,159
2. Zhiqian Zhao, Yongliang Li*, Guilei Wang, et al., A novel three-layer graded SiGe strain relaxed buffer for the high crystal quality and strained Si0.5Ge0.5 layer epitaxial grown. Journal of Materials Science: Materials in Electronics, 2019, 30, 14130
3. Zhiqian Zhao, Yongliang Li*, Guilei Wang, et al., Process optimization of the Si0.7Ge0.3 Fin Formation for the STI first scheme. Semicond. Sci. Technol., 2019, 34, 125008
4. Zhiqian Zhao, Xiaohong Cheng, Yongliang Li*, et al., Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device. Journal of Materials Science: Materials in Electronics, 2020, 31(8),5854
5. Yongliang Li, Xiaohong Cheng, Zhaoyang Zhong, et al., Key Process Technologies for Stacked Double Si0.7Ge0.3 Channel Nanowires Fabrication. ECS Journal of Solid State Science and Technology, 2020, 9, 064009
6. Xiaohong Cheng, Yongliang Li*, Guilei Wang, et al., Investigation on thermal stability of Si0.7Ge0.3/Si stacked multilayer for gate-all-around MOSFETS. Semicond. Sci. Technol., 2020, 35(11), 115008-1-5
7. Xiaohong Cheng, Yongliang Li*, Haoyan Liu, et al., Selective wet etching in fabricating SiGe nanowires with TMAH solution for gate-all-around MOSFETs. Journal of Materials Science: Materials in Electronics, 2020, 31, 22478
8. Haoyan Liu, Yongliang Li*, Xiaohong Cheng, et al., Fabrication and selective wet etching of Si0.2Ge0.8/Ge multilayer for Si0.2Ge0.8 channel gate-all-around MOSFETs. Materials Science in Semiconductor Processing, 2021, 121, 105397
9. Yongliang Li, Fei Zhao, Xiaohong Cheng, et al., Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics. Nanomaterials, 2021, 11(7), 1689
10. Yongliang Li, Fei Zhao, Xiaohong Cheng, et al., Integration of Si0.7Ge0.3 fin onto a bulk-Si substrate and its P-type FinFET device fabrication. Semicond. Sci. Technol. 2021, 36, 125001
已授权專利：
1. 李永亮，王文武，一种半导体结构及其制备方法，授权公告号：CN 109003902 B
2. 李永亮，程晓红等，一种堆叠纳米线或片CMOS器件制备方法，授权公告号：CN 110729248 B
3. Yongliang Li, Xiaohong Cheng. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, 授权公告号: US11024708 B1.
4. Yongliang Li, Qiuxia Xu. Method for etching Mo-based metal gate stack with Aluminium nitride barrier, 授权公告号: US20110263114.
5. Qiuxia Xu, Yongliang Li. Manufacturing method for structure of metal gate/ high k gate dielectric stack layer，授权公告号US20110256704.
6. Qiuxia Xu, Yongliang Li. Method for manufacturing metal gate stack structure in gate-first process, 授权公告号：US20120003827.
7. Qiuxia Xu, Yongliang Li, Gaobo Xu. Method for manufacturing CMOS FET, 授权公告号： US20130078773.
8. Qiuxia Xu, Yongliang Li. Method for manufacturing a metal gate electrode/high K dielectric gate stack，授权公告号：US20110256704.
9. Qiuxia Xu, Yongliang Li. Method for removing polymer after etching gate stack structure of high-k gate dielectric/metal gate, 授权公告号：US8334205.
10. 李永亮, 徐秋霞,一种选择性去除TaN金属栅材料的方法，授权公告号：CN101656208 A.
中科院尊龙凯时優秀員工一次
中國科學院院长优秀奖一次
中國科學院朱李月华奖一次
人才隊伍